This patent application relates to the field of circuit simulation, and more precisely to enabling circuit designers to more easily and immediately visualize the effects of parameter changes on parameterized cells.
Circuit designers often use parameterized cells or “Pcells” to efficiently create a circuit design. A Pcell is defined in this application as a parameterized and programmable cell that allows a user to dynamically create a customized circuit design according to a set of specified Pcell parameters. A Pcell thus represents a part of a circuit that is not a fixed element. The term “Pcell” also encompasses other descriptors that may be used by a variety of commercial circuit design tool vendors for their various implementations of parameterized and programmable cells.
A given Pcell may be instantiated in a design many times, sometimes as part of a hierarchical design process used to help manage design complexity and to increase designer productivity. Different instances may have different parameter values. Customized circuit designs may thus be created simply by providing different Pcell parameter values in different cell instances. For example, a designer may create a transistor cell and then use different instances of the same cell with different specified widths, lengths, and other governing parameters to create different transistors. Pcells are often implemented in source code, and commercially offered software programs are available from different vendors for executing this source code.
The instantiation of a Pcell may cause the addition of program-created circuitry to a circuit schematic, and/or trigger the construction of a corresponding layout geometry that will be used to control its manufacture. Parameter values may therefore influence the electrical behavior of the circuit as well as its layout.
Once the layout of a circuit is finished, it is checked to make sure it satisfies the design rules, which are typically provided by an integrated circuit foundry. Design rules describe minimum distances, sizes, enclosure criteria, and other constraints for implementing the layout properly. Design rules are not specific for any particular integrated circuit, but are instead applied to all designs to be processed using a particular process technology. In modern submicron integrated circuitry, the electrical behavior and physical layout of circuits can be tightly interrelated. As a result, the design rules governing integrated circuit structures are often complex. Commercial software programs are therefore available to perform design rule checking Layout changes may be required for all design rule checks to be met.
While parameterized programmable cell-based designs are powerful when properly managed, with conventional software tools Pcell-based designs may only be edited via their parameters. As a result, circuit designers cannot necessarily quickly and easily see and conceptually correlate the results of parameter value changes on Pcells. A clear intuitive design relationship between parameter changes and circuit behavior and layout geometry is often lacking.
Also, Pcell tools do not always check parameter value validity, nor do the tools accept the setting of ranges of parameter values. A user may therefore provide an unrealistic value for a parameter but no immediate invalidation for it occurs. Design problems may therefore persist for some time until the root of the problem is discerned.
Finally, when a user is testing different parameter values, focus is constantly switching between the parameter editing form and the graphic display window depicting layout results. This loss of focus makes it difficult for the user to recognize what has changed in the Pcell design being displayed. Accordingly, the inventors have developed a novel way to use continuous parameter value updates to rapidly evaluate a programmable cell.